A recent development of semiconductors contributes to rapid growth of handheld systems such as handheld phones, personal digital assistants and so on. To achieve such equipment in an economical manner, it is highly required to develop high performance and multi-function devices such as high density integrated circuits (ICs) and multiple integration of MOS (Metal oxide semiconductor) transistors and bipolar transistors.
Designing fabrication process of well structures is a key to obtain the high performance and multi-function devices. A twin-well structure has been widely used and a triple-well structure has been introduced for fabricating compact and multi-function devices. The triple-well structure makes it possible to mount circuits working with a minus power supply voltage and contributes a large reduction of noises. Therefore, the triple-well structure is commonly used in LSI (large scale integrated circuit) including analog and digital circuits and memory ICs.
A variety of methods to form the triple-well structure has been proposed. In one method, a P-well is formed in a N-type substrate, a dose of N-type impurities is applied into the P-well by ion implantation and an N-well is formed at another area of the P-well in the same process of forming the N-well. With this process, it is possible to form a triple-well structure without an additional process in comparison with the twin-well process. However, a concentration of the N-well formed at another area of the P-well is different from a concentration of the N-well formed in the P-well.
Namely, the concentrations of the wells have a relationship D1>D2>D3, where D1 is the N-type impurity concentration of the N-well formed at the other area of the P-well, D2 is the P-type impurity concentration of P-well and D3 is the N-type impurity concentration of the N-well formed in the P-well. Thus, by this method, it is not possible to form the N-wells with the equivalent N-type impurity concentration. Due to the different N-type impurity concentration of the N-well in the P-well, transistors in the N-wells have different electrical characteristics from each other. As a result, it is difficult and complicated to design circuits using the transistors having different electrical characteristics.
Another proposed method is to use two masks having openings at different positions and form N-wells at separate processes using the masks. However, a number of masks increases with an increase of a number of wells. Consequently a fabrication cost is becoming highly proportional to the number of masks and processes.
As another method, it is proposed to introduce high energy ion implantation method. FIG. 1 illustrates a cross-sectional view of the semiconductor having triple-well structure formed by this method. In this method, a P-well 232 making a frame border is formed in a substrate 230. Then a P-type impurity is implanted with high energy ion in a deep portion in the substrate 230. Then, diffusion and activation processes are performed such that a buried P-well 236 is formed in contact with a bottom of P-well 232 as shown in FIG. 1.
Then, an N-type impurity is implanted at a surface of an area which is surrounded with the P-well 232 and the buried P-well 236. At the same time, a N-type impurity is also implanted at another area which is not surrounded with the P-well 232 and the buried P-well 236. Then, diffusion and activation process are performed such that N-wells 238 and 240 are formed.
Because the N-well 238 is surrounded with the P-well 232 and the buried P-well 236, the N-well 238 is electrically disconnected to the substrate 230 and the N-wells 240. Moreover, the N-wells 238 and 240 are formed at the same process and with the same dosage of N-type impurity. As a result, N-wells having same impurity concentration are formed inside and outside of the area which is surrounded with the P-well 232 and the buried P-well 236.
The high energy ion implantation method requires one more photo-lithography process to twin-well process. Adding one process, it is possible to form a triple-well which includes the deep P-well (DPW) consisting of the P-well 232 and the buried P-well 236 and the N-well 238 surrounded with the DPW. Moreover, it is possible that each transistor formed in each well has a same electrical characteristic because the wells are formed to have the same impurity concentration. Therefore, it becomes easy to perform a circuit design with a simple transistor lineup to be used.
However, the high energy ion implantation method requires an expensive high energy ion implantation apparatus. Therefore, it is desired to form a triple-well structure associated with wells having uniform impurity concentration inside and outside of the triple-well structure by a simple and a high cost performance fabrication process without using high energy ion implantation equipment.